SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology
A modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circui...
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IEEE
2025-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10839490/ |
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| author | Rajiv V. Joshi J. Frougier Alberto Cestero Crystal Castellanos Sudipto Chakraborty Carl Radens M. Silvestre S. Lucarini I. Ahsan E. Leobandung |
| author_facet | Rajiv V. Joshi J. Frougier Alberto Cestero Crystal Castellanos Sudipto Chakraborty Carl Radens M. Silvestre S. Lucarini I. Ahsan E. Leobandung |
| author_sort | Rajiv V. Joshi |
| collection | DOAJ |
| description | A modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45 V with an estimated margin/speed of 6 GHz for SRAM cells (high density—<inline-formula> <tex-math notation="LaTeX">$0.026~\mu $ </tex-math></inline-formula>m<sup>2</sup>, and high current—<inline-formula> <tex-math notation="LaTeX">$0.032~\mu $ </tex-math></inline-formula>m<sup>2</sup>). |
| format | Article |
| id | doaj-art-ce52f5422b6b44e48a0d4fd5f372d9c1 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-ce52f5422b6b44e48a0d4fd5f372d9c12025-02-12T00:03:01ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492025-01-015607410.1109/OJSSCS.2024.352449510839490SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet TechnologyRajiv V. Joshi0https://orcid.org/0009-0007-7486-1531J. Frougier1Alberto Cestero2Crystal Castellanos3https://orcid.org/0009-0004-3947-1157Sudipto Chakraborty4https://orcid.org/0000-0001-9884-5850Carl Radens5https://orcid.org/0009-0008-8877-6888M. Silvestre6S. Lucarini7I. Ahsan8E. Leobandung9Hybrid Cloud, IBM T. J. Watson Research Center, Yorktown Heights, NY, USAHybrid Cloud, IBM Research Center, Albany, NY, USAHybrid Cloud, IBM Research Center, Albany, NY, USAIBM Infrastructure, IBM, Rochester, MN, USAHybrid Cloud, IBM T. J. Watson Research Center, Yorktown Heights, NY, USAHybrid Cloud, IBM Research Center, Albany, NY, USAHybrid Cloud, IBM Research Center, Albany, NY, USAHybrid Cloud, IBM Research Center, Albany, NY, USAHybrid Cloud, IBM Research Center, Albany, NY, USAHybrid Cloud, IBM T. J. Watson Research Center, Yorktown Heights, NY, USAA modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45 V with an estimated margin/speed of 6 GHz for SRAM cells (high density—<inline-formula> <tex-math notation="LaTeX">$0.026~\mu $ </tex-math></inline-formula>m<sup>2</sup>, and high current—<inline-formula> <tex-math notation="LaTeX">$0.032~\mu $ </tex-math></inline-formula>m<sup>2</sup>).https://ieeexplore.ieee.org/document/10839490/Compute-in-memory (CIM)Gate all around (GAA)low Vminnanosheet (NS)read assistSRAM |
| spellingShingle | Rajiv V. Joshi J. Frougier Alberto Cestero Crystal Castellanos Sudipto Chakraborty Carl Radens M. Silvestre S. Lucarini I. Ahsan E. Leobandung SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology IEEE Open Journal of the Solid-State Circuits Society Compute-in-memory (CIM) Gate all around (GAA) low Vmin nanosheet (NS) read assist SRAM |
| title | SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology |
| title_full | SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology |
| title_fullStr | SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology |
| title_full_unstemmed | SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology |
| title_short | SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology |
| title_sort | sram and mixed signal logic with noise immunity in 3 nm nano sheet technology |
| topic | Compute-in-memory (CIM) Gate all around (GAA) low Vmin nanosheet (NS) read assist SRAM |
| url | https://ieeexplore.ieee.org/document/10839490/ |
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