Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators
Three-dimensional heterogeneous integration (3D-HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, addressing the need for on-chip acceleration of large AI models. However, this approach faces challenges with...
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IEEE
2025-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10854426/ |
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| author | Madison Manley James Read Ankit Kaul Shimeng Yu Muhannad Bakir |
| author_facet | Madison Manley James Read Ankit Kaul Shimeng Yu Muhannad Bakir |
| author_sort | Madison Manley |
| collection | DOAJ |
| description | Three-dimensional heterogeneous integration (3D-HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, addressing the need for on-chip acceleration of large AI models. However, this approach faces challenges with power supply noise (PSN) margins due to <inline-formula> <tex-math notation="LaTeX">$V_{\text {DD}}$ </tex-math></inline-formula> scaling and increased power delivery network (PDN) impedance. This study demonstrates the necessity and benefits of 3D-HI for large-scale CIM accelerators, where 2-D implementations would exceed manufacturing reticle limits. Our 3-D designs achieve 39% higher energy efficiency, <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> higher operation density, and improved throughput through shorter vertical interconnects. We quantify steady-state IR-drop impacts in 3D-HI CIM architectures using a framework that combines PDN modeling, 3D-HI power, performance, area estimation, and behavioral modeling. We demonstrate that a drop in supply voltage to CIM arrays increases sensitivity to process, voltage, and temperature (PVT) noise. Using our framework, we model IR-drop and simulate its impact on the accuracy of ResNet-50 and ResNet-152 when classifying images from the ImageNet 1k dataset in the presence of injected PVT noise. We analyze the impact of through-silicon via (TSV) design and placement to optimize the IR-drop and classification accuracy. For ResNet architectures in 3-D integration, we demonstrate that peripheral TSV placement provides an optimal balance between interconnect complexity and performance, achieving IR-drop below 10% of <inline-formula> <tex-math notation="LaTeX">$V_{\text {DD}}$ </tex-math></inline-formula> while maintaining high classification accuracy. |
| format | Article |
| id | doaj-art-fe1643ab903149a4aaf823c043b8dfd8 |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-fe1643ab903149a4aaf823c043b8dfd82025-02-11T00:01:42ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312025-01-0111101810.1109/JXCDC.2025.353456010854426Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory AcceleratorsMadison Manley0https://orcid.org/0000-0002-9051-7518James Read1https://orcid.org/0000-0003-0753-6257Ankit Kaul2https://orcid.org/0000-0003-0301-1349Shimeng Yu3https://orcid.org/0000-0002-0068-3652Muhannad Bakir4Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USADepartment of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USADepartment of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USADepartment of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USADepartment of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USAThree-dimensional heterogeneous integration (3D-HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, addressing the need for on-chip acceleration of large AI models. However, this approach faces challenges with power supply noise (PSN) margins due to <inline-formula> <tex-math notation="LaTeX">$V_{\text {DD}}$ </tex-math></inline-formula> scaling and increased power delivery network (PDN) impedance. This study demonstrates the necessity and benefits of 3D-HI for large-scale CIM accelerators, where 2-D implementations would exceed manufacturing reticle limits. Our 3-D designs achieve 39% higher energy efficiency, <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> higher operation density, and improved throughput through shorter vertical interconnects. We quantify steady-state IR-drop impacts in 3D-HI CIM architectures using a framework that combines PDN modeling, 3D-HI power, performance, area estimation, and behavioral modeling. We demonstrate that a drop in supply voltage to CIM arrays increases sensitivity to process, voltage, and temperature (PVT) noise. Using our framework, we model IR-drop and simulate its impact on the accuracy of ResNet-50 and ResNet-152 when classifying images from the ImageNet 1k dataset in the presence of injected PVT noise. We analyze the impact of through-silicon via (TSV) design and placement to optimize the IR-drop and classification accuracy. For ResNet architectures in 3-D integration, we demonstrate that peripheral TSV placement provides an optimal balance between interconnect complexity and performance, achieving IR-drop below 10% of <inline-formula> <tex-math notation="LaTeX">$V_{\text {DD}}$ </tex-math></inline-formula> while maintaining high classification accuracy.https://ieeexplore.ieee.org/document/10854426/3-D heterogeneous integration (3D-HI)compute-in-memory (CIM)emerging nonvolatile memory (eNVM)IR-droppower delivery network (PDN)RRAM reliability |
| spellingShingle | Madison Manley James Read Ankit Kaul Shimeng Yu Muhannad Bakir Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3-D heterogeneous integration (3D-HI) compute-in-memory (CIM) emerging nonvolatile memory (eNVM) IR-drop power delivery network (PDN) RRAM reliability |
| title | Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators |
| title_full | Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators |
| title_fullStr | Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators |
| title_full_unstemmed | Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators |
| title_short | Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators |
| title_sort | co optimization of power delivery network design for 3 d heterogeneous integration of rram based compute in memory accelerators |
| topic | 3-D heterogeneous integration (3D-HI) compute-in-memory (CIM) emerging nonvolatile memory (eNVM) IR-drop power delivery network (PDN) RRAM reliability |
| url | https://ieeexplore.ieee.org/document/10854426/ |
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